Scalable Parasitic Components Model of CMOS for RF Circuit Design

Nobuyuki ITOH
Tatsuya OHGURO
Kazuhiro KATOH
Shin-ichiro ISHIZUKA

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A    No.2    pp.288-298
Publication Date: 2003/02/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
CMOS,  model,  substrate,  high-frequency,  s-parameter,  

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A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.

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