3.3 V 35 mW Second-Order Three-Bit Quadrature Band-Pass ΔΣ Modulator for Digital Radio

Hack-Soo OH  Chang-Gene WOO  Pyung CHOI  Geunbae LIM  Jang-Kyoo SHIN  Jong-Hyun LEE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.12   pp.3230-3239
Publication Date: 2003/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
Keyword: 
digital radio,  band-pass delta-sigma modulation,  switched-capacitor circuit,  IF signal,  analog-digital conversion,  

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Summary: 
Delta-sigma modulators (DSMs) are commonly use in high-resolution analog-to-digital converters, and band-pass delta-sigma modulators have recently been used to convert IF signals into digital signals. In particular, a quadrature band-pass delta-sigma modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. The current paper proposes a second-order three-bit quadrature band-pass delta-sigma modulator that can achieve a lower power consumption and better performance with a similar die size to a conventional fourth-order quadrature band-pass delta-sigma modulator (QBPDSM). The proposed system is integrated using CMOS 0.35 µm, double-poly, four-metal technology. The system operates at 13 MHz and can digitize a 200 kHz bandwidth signal centered at 4.875 MHz with an SNR of 85 dB. The power consumption is 35 mW at 3.3 V and 38 mW at 5 V, and the die size is 21.9 mm2.