IEICE Trans - Evaluation of Delay Testing Based on Path Selection

Evaluation of Delay Testing Based on Path Selection

Masayasu FUKUNAGA  Seiji KAJIHARA  Sadami TAKEOKA  Shinichi YOSHIMURA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.12   pp.3208-3210
Publication Date: 2003/12/01
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword:
delay testing,  path delay fault,  path selection,  untestable path,

Full Text: PDF>>

Summary:
Since a logic circuit often has too many paths to test delay of all paths, it is necessary for path delay testing to limit the number of paths to be tested. The paths to be tested should have large delay because such paths more likely cause a fault. Additionally, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate two typical criteria of path selection for path delay testing. From our experiments, we observe that test patterns for the longest paths cannot cover many local delay defects such as transition faults.