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A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Hideyuki ICHIHARA Tomoo INOUE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
test generation, acyclic sequential circuits, stuck-at fault, partial scan, multiple fault,
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A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.