DFT Timing Design Methodology for Logic BIST

Yasuo SATO  Motoyuki SATO  Koki TSUTSUMIDA  Kazumi HATAYAMA  Kazuyuki NOMOTO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.12   pp.3049-3055
Publication Date: 2003/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
DFT,  at-speed BIST,  timing design,  multiple-clock,  

Full Text: PDF(635.5KB)>>
Buy this Article




Summary: 
We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built-in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.