A Low Power Embedded DRAM Macro for Battery-Operated LSIs

Takeshi FUJINO  Akira YAMAZAKI  Yasuhiko TAITO  Mitsuya KINOSHITA  Fukashi MORISHITA  Teruhiko AMANO  Masaru HARAGUCHI  Makoto HATAKENAKA  Atsushi AMO  Atsushi HACHISUKA  Kazutami ARIMOTO  Hideyuki OZAKI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A    No.12    pp.2991-3000
Publication Date: 2003/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
embedded memory,  DRAM,  low power,  system on chip,  

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A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm2 CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.