Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays

Sadahiro TANI  Yoshihiro UCHIDA  Makoto FURUIE  Shuji TSUKIYAMA  BuYeol LEE  Shuji NISHI  Yasushi KUBOTA  Isao SHIRAKAWA  Shigeki IMAI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.12   pp.2923-2932
Publication Date: 2003/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
interconnect,  LCD,  parasitic capacitance,  signal integrity,  circuit simulation,  

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The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.