Statistical Gate-Delay Modeling with Intra-Gate Variability

Kenichi OKADA  Kento YAMAOKA  Hidetoshi ONODERA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E86-A   No.12   pp.2914-2922
Publication Date: 2003/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
intra-chip variability,  statistical timing analysis,  intra-gate variability,  manufacturing fluctuation,  

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This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.