Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme

Woo-Chan PARK  Cheol-Ho JEONG  Tack-Don HAN  

IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.8   pp.1341-1345
Publication Date: 2002/08/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System Element
computer arithmetic,  floating-point unit,  floating-point adder,  

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The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.