Design for Hierarchical Two-Pattern Testability of Data Paths

Md. Altaf-Ul-AMIN  Satoshi OHTAKE  Hideo FUJIWARA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.6   pp.975-984
Publication Date: 2002/06/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerance
Keyword: 
design for testability,  delay testing,  hierarchical testability,  two-pattern testability,  

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Summary: 
This paper introduces the concept of hierarchical testability of data paths for delay faults. A definition of hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to become an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide similar advantages to the enhanced scan approach at a much lower hardware overhead cost.