For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA Koji NAKAMAE Hiromu FUJIOKA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
EB tester, line delay fault, fault localization, layout analysis, combinational circuits,
Full Text: PDF>>
The EB tester line delay fault localization algorithm for combinational circuits is proposed where line delay fault probabilities are utilized to narrow fault candidates down to one efficiently. Probabilities for two main causes of line delay faults, defects of contact/vias along interconnections and crosstalk, are estimated through layout analysis. The algorithm was applied to 8 kinds of ISCAS'85 benchmark circuits to evaluate its performance where the guided probe (GP) diagnosis was used as the reference method. The proposed method can cut the number of probed lines to about 30% in average compared with those for the GP method. The total fault localization time was 31% of the time for the GP method and was 6% less than that of our previous method where the fault list generated in concurrent fault simulation is utilized.