EB-Testing-Pad Method and its Evaluation by Actual Devices

Norio KUJI  Takako ISHIHARA  Shigeru NAKAJIMA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.10   pp.1558-1563
Publication Date: 2002/10/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
E-beam tester,  observability,  stacked vias,  testing pads,  multi level wiring,  

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Summary: 
A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.