IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

Masaki HASHIZUME  Teppei TAKEDA  Masahiro ICHIMIYA  Hiroyuki YOTSUYANAGI  Yukiya MIURA  Kozo KINOSHITA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.10   pp.1534-1541
Publication Date: 2002/10/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
IDDQ sensor,  CMOS,  IDDQ test,  bridging fault,  

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Summary: 
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.