IEICE Trans - High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model

Michinobu NAKAO  Yoshikazu KIYOSHIGE  Yasuo SATO  Kazumi HATAYAMA  Satoshi FUKUMOTO  Kazuhiko IWASAKI

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.10   pp.1506-1514
Publication Date: 2002/10/01
Online ISSN:
DOI:
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword:
delay testing,  path selection,  fault simulation,  test generation,  path-status graph,

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Summary:
This paper presents a practical fault model for delay testing, called a multiple-threshold gate-delay fault model, to obtain high quality tests that guarantee the detection of delay faults for various extra-delays. Fault efficiencies for multiple thresholds of the extra-delay are introduced as a coverage metric that describes the quality of tests. Our approach guarantees that each gate-delay fault is tested on the path that is almost the longest one passing through the faulty line by using two-pattern tests with pattern-independent timing. We present the procedures of the path selection, fault simulation, and the test generation, where the path-status graph technique is used as not to rely on the enumeration of paths. Experimental results for benchmark circuits demonstrate that the proposed metric gives useful information that transition fault efficiency cannot, and that the proposed test generation can achieve high fault efficiencies for multiple-threshold gate-delay faults.