Accomplishment of At-Speed BISR for Embedded DRAMs

Yoshihiro NAGURA  Yoshinori FUJIWARA  Katsuya FURUE  Ryuji OHMURA  Tatsunori KOMOIKE  Takenori OKITAKA  Tetsushi TANIZAKI  Katsumi DOSAKA  Kazutami ARIMOTO  Yukiyoshi KODA  Tetsuo TADA  

IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.10   pp.1498-1505
Publication Date: 2002/10/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
at-speed test,  BISR,  embedded DRAM,  test cost reduction,  

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The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.