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Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
hybrid BIST, unmodeled fault, n-detection test, partially rotational scan, at-speed testing,
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An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.