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Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
test generation, test plans, compacted test plan tables, test plan compatibility graph, RTL data path,
Full Text: PDF(1.2MB)>>
This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.