A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller

Akira YAMAZAKI
Takeshi FUJINO
Kazunari INOUE
Isamu HAYASHI
Hideyuki NODA
Naoya WATANABE
Fukashi MORISHITA
Katsumi DOSAKA
Yoshikazu MOROOKA
Shinya SOEDA
Kazutami ARIMOTO
Setsuo WAKE
Kazuyasu FUJISHIMA
Hideyuki OZAKI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C    No.9    pp.1697-1708
Publication Date: 2002/09/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAM,  system on chip,  3-D graphics concurrent operation,  

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Summary: 
A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.