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A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters
Masanori FURUTA Shoji KAWAHITO Daisuke MIYAZAKI
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)
pipelined ADC, parallel pipelined ADC, digital calibration, error measurement,
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A digital calibration technique, which corrects errors due to capacitor mismatch in pipelined ADC and directly measures the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.5 dB, a peak integral non-linearity of 0.3 LSB, and a peak differential non-linearity of 0.3 LSB using the digital calibration.