Clock Feedthrough Reduction of CMOS Autozeroed Operational Amplifiers by Two-Stage Self-Compensation

Hidekuni TAKAO  Fumie INA  Kazuaki SAWADA  Makoto ISHIDA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C    No.7    pp.1499-1505
Publication Date: 2002/07/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
operational amplifier,  autozeroing,  clock feedthrough,  offset drift,  

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Summary: 
In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.