A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits

Norio KOIKE
Hirokazu YONEZAWA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C    No.6    pp.1356-1366
Publication Date: 2002/06/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
hot carrier,  secondary hot electron,  simulation,  

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Summary: 
A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional τId/W-Isub/Id model.