For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier
Sang-Hoon LEE Seung-Jun BAE Hong-June PARK
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/06/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
parallel multiplier, redundant binary, radix-64, CMOS circuit, digital circuit,
Full Text: PDF>>
The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm2. The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.