Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation

Daisuke NOTSU  Naoya IKECHI  Yasuyuki AOKI  Nobuyuki KAWAKAMI  Kentaro SHIBAHARA  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.5   pp.1119-1124
Publication Date: 2002/05/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
LOCOS,  junction leakage current,  PSL,  isolation,  bird's beak,  

Full Text: PDF(281.5KB)>>
Buy this Article

We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.