Silicon Resonant Tunneling Metal-Oxide-Semiconductor Transistor for Sub-0.1 µm Era

Naoto MATSUO  Yoshinori TAKAMI  Takahiro NOZAKI  Hiroki HAMADA  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.5   pp.1086-1090
Publication Date: 2002/05/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
SRTMOST,  sub-0.1 µm,  logic circuit,  

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The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.