Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs

Toshiki SAITO  Takuya SARAYA  Takashi INUKAI  Hideaki MAJIMA  Toshiharu NAGUMO  Toshiro HIRAMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.5   pp.1073-1078
Publication Date: 2002/05/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
SOI MOSFET,  triangular wire,  short channel effect,  subthreshold factor,  DIBL,  

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We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.