Subband Structure Engineering for Realizing Scaled CMOS with High Performance and Low Power Consumption

Shin-ichi TAKAGI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.5   pp.1064-1072
Publication Date: 2002/05/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
Category: 
Keyword: 
inversion layer,  mobility,  subband,  strained-Si,  SOI,  

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Summary: 
Enhancement of inversion-layer mobility and inversion-layer capacitance becomes more important in realizing scaled CMOS, from both viewpoints of higher performance and lower power consumption. This paper presents an engineering scenario of the subband structure in inversion layer for the enhancement of inversion-layer mobility and capacitance in MOSFETs. A key factor for the electron mobility enhancement is to increase the energy difference in the subband energy between the two-fold and the four-fold valleys and the resultant electron occupancy of the two-fold valleys. The electrical characteristics of two device structures based on this subband engineering, strained-Si MOSFETs and ultra-thin SOI MOSFETs, are studied. Also, it is shown that the reduction in SOI films down to less than inversion-layer thickness of bulk MOSFETs is an effective way to increase inversion-layer capacitance.