A 100 nm Node CMOS Technology for System-on-a-Chip Applications

Kiyotaka IMAI  Atsuki ONO  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.5   pp.1057-1063
Publication Date: 2002/05/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
CMOS,  threshold voltage,  gate leakage current,  oxynitride,  

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We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.