Design of Demultiplexer and Demonstration of the Operation up to 46 GHz

Futoshi FURUTA
Kazuo SAITOH
Kazumasa TAKAGI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C    No.3    pp.631-635
Publication Date: 2002/03/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
Keyword: 
demultiplexer (DMUX),  SFQ,  binary tree,  Monte Carlo,  

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Summary: 
We have designed a demultiplexer (DMUX) with a simple structure, high-speed operation circuits and large bias margins. By using a binary-tree architecture and clock-driven circuits, multi-channel DMUXs can be constructed easily from the same elemental circuits, i.e., 1-to-2 DMUX, consisting of a T-FF and a 1-to-2 switch. By applying cell-level optimization and Monte Carlo simulation, bias margins and operation frequency of the circuits were enlarged. Logical operations of the 1-to-2 DMUX and a multi-channel DMUX, e.g., a 1-to-4 DMUX were experimentally confirmed. It was also confirmed that the large margins, 33% of the DMUX (1-to-2 switch) was kept up regardless the degree of integration, and that the 1-to-2 DMUX can operate up to 46 GHz by using measure of average voltages across Josephson junctions.