IEICE Trans - 50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing

50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing

Lizhen ZHENG  Xiaofan MENG  Stephen WHITELEY  Theodore Van DUZER

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.3   pp.621-624
Publication Date: 2002/03/01
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
Keyword:
superconductive digital circuits,  single-flux-quantum circuit,  multiplexer,  demultiplexer (DMUX),

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Summary:
We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm² and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.