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Low Spurious Frequency Setting Algorithm for a Triple Tuned Type PLL Synthesizer Driven by a DDS
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Issue on Signals, Systems and Electronics Technology)
direct digital synthesizer, phase locked loop, spurious component, triple tune,
Full Text: PDF(405.5KB)>>
This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.