Design and Experimental Results of CMOS Low-Noise/Driver MMIC Amplifiers for Use in 2.4-GHz and 5.2-GHz Wireless Communications

Kazuya YAMAMOTO  Tetsuya HEIMA  Akihiko FURUKAWA  Masayoshi ONO  Yasushi HASHIZUME  Hiroshi KOMURASAKI  Hisayasu SATO  Naoyuki KATO  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.2   pp.400-407
Publication Date: 2002/02/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Microwaves, Millimeter-Waves
Si-bulk CMOS,  MMIC,  2.4 GHz,  5.2-GHz,  low-noise/driver amplifier,  

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This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.