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Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications
Johannes KNEIP Matthias WEISS Wolfram DRESCHER Volker AUE Jurgen STROBEL Thomas OBERTHUR Michael BOLLE Gerhard FETTWEIS
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Product Designs
wireless LAN, IEEE 802.11, HiperLAN/2, programmable DSP, SIMD processor, WLAN ASSP,
Full Text: PDF(1.5MB)>>
This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.