A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications

Tetsuya YAMADA  Makoto ISHIKAWA  Yuji OGATA  Takanobu TSUNODA  Takahiro IRITA  Saneaki TAMAKI  Kunihiko NISHIYAMA  Tatsuya KAMEI  Ken TATEZAWA  Fumio ARAKAWA  Takuichiro NAKAZAWA  Toshihiro HATTORI  Kunio UCHIYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E85-C    No.2    pp.253-262
Publication Date: 2002/02/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
embedded processor,  low power,  RISC,  DSP,  MAC,  

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A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.