A 500-MHz Embedded Out-of-Order Superscalar Microprocessor

Masayuki DAITO  Kazumasa SUZUKI  Ken-ichi UEHIGASHI  Hiroshi MORITA  Hitoshi SONODA  Nobuhito MORIKAWA  Masatoshi MORIYAMA  Shoichiro SATO  Terumi FUKUDA  Saori NAKAMURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.2   pp.243-252
Publication Date: 2002/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processor,  RISC,  out-of-order,  superpipeline,  

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Summary: 
A MIPS-architecture-based embedded out-of-order superscalar microprocessor targeting broadband applications has been developed. Aggressive microarchitectures, such as superpipelining and out-of-order execution, have been applied to realize better performance scalability in order to fit with next-generation broadband applications. The chip includes a 32 K-Byte instruction cache, a 32 K-Byte data cache, 6 independent execution units, and has been designed using an ASIC-style design methodology on a 0.13-µm CMOS 5-layer aluminum technology. It can operate up to 500 MHz and achieves 1005 MIPS (Dhrystone 2.1) at 500-MHz operation.