A Simplified Dopant Pile-Up Model for Process Simulators

Hirokazu HAYASHI  Noriyuki MIURA  Hirotaka KOMATSUBARA  Marie MOCHIZUKI  Koichi FUKUDA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.12   pp.2117-2122
Publication Date: 2002/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
RSCE,  simple model,  dopant pile-up,  threshold voltage,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.