For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/10/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
interconnection problem, pass-transistor network, functional pass gate, multiple-valued logic, content-addressable memory,
Full Text: PDF(1.5MB)>>
This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.