Ethernet Over HDLC Forwarding VLSI for Network Access System

Minsuk HONG  Jinsung OH  Chan Young PARK  Wooseok KANG  Sehyeon RHEE  Sang-Hui PARK  

IEICE TRANSACTIONS on Communications   Vol.E85-B   No.7   pp.1382-1385
Publication Date: 2002/07/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Communication Devices/Circuits
forwarding,  Ethernet,  HDLC,  MAC,  

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In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.