Sidelobe Level of a Two-Bit Digital Phased Array Composed of a Small Number of Elements

Masaharu FUJITA  

Publication
IEICE TRANSACTIONS on Communications   Vol.E85-B   No.5   pp.982-986
Publication Date: 2002/05/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Wireless Communications Issue)
Category: 
Keyword: 
digital phased array,  two-bit phase shifter,  sidelobe reduction,  quadratic-phase feed,  

Full Text: PDF>>
Buy this Article



Summary: 
This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.