For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Design for a Turbo-Code Decoder Using a Block-Wise Algorithm
Goo-Hyun PARK Suk-Hyon YOON Daesik HONG Chang-Eon KANG
IEICE TRANSACTIONS on Communications
Publication Date: 2002/02/01
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Wireless Communication Technology
turbo-codes decoder, MAP algorithm, Max-Log-MAP algorithm, block-wise algorithm,
Full Text: PDF>>
Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.