Loop and Address Code Optimization for Digital Signal Processors

Jong-Yeol LEE  In-Cheol PARK  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A   No.6   pp.1408-1415
Publication Date: 2002/06/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Digital Signal Processing
digital signal processor (DSP),  compiler,  code optimization,  

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This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.