Recognition of Floorplan by Parametric BSG for Reuse of Layout Design

Keishi SAKANUSHI  Zhonglin WU  Yoji KAJITANI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A   No.4   pp.872-879
Publication Date: 2002/04/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
parametric BSG,  layout,  reuse,  floorplan,  technology migration,  

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In reuse of the VLSI layout design when technology migration takes place, the information to be abstracted from the original design and the data structure to store the information shall be specified. In this paper, they are assumed as the seg-based 4-direction and the parametric BSG, respectively. The parametric BSG is a BSG whose segs are generalized to take any number of units of length. The seg-based 4-direction is the right-of, left-of, above, and below relations between two rooms in accordance with the segs between them. An elegant procedure is given to map the floorplan of the model into a parametric BSG of the minimum size, keeping the abstracted seg-based 4-direction. Merits of the PBSG are discussed and a way of reuse is suggested by illustrative instances. Finally, a superior potential of the parametric BSG as the data structure is discussed empirically.