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A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention
Sungkyung PARK Changsik YOO Sin-Chong PARK
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Circuit Theory
four-state dynamic phase detector, harmonic locking, DLL,
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A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.