Increase in Delay Uncertainty by Performance Optimization

Masanori HASHIMOTO  Hidetoshi ONODERA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A   No.12   pp.2799-2802
Publication Date: 2002/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimization,  delay increase,  statistical timing analysis,  delay uncertainty,  transistor sizing,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay times of long paths are shortened and the delay times of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which is caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of circuit delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.