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Characterization and Computation of Steiner Routing Based on Elmore's Delay Model
Satoshi TAYU Mineo KANEKO
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E85A
No.12
pp.27642774 Publication Date: 2002/12/01
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: Elmore's delay, Steiner tree, net, binary tree, Manhattan distance,
Full Text: PDF(1.2MB)>>
Summary:
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize signal delays in digital VLSIs. There are a number of ways to evaluate a signal delay of a net, such as cost, radius, and Elmore's delay. Delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. So, it is important to investigate the properties of this model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We show the effectiveness of our proposed algorithm by comparing ERT algorithm which is proposed in [2] for minimizing the maximum Elmore's delay of a sink. Our proposed algorithm decreases the average of the maximum Elmore's delay by 1020% for ERT algorithm. We also compare our algorithm with an O(n^{4}) algorithm proposed in [15] and confirm the effectiveness of our algorithm though its time complexity is O(n^{3}).

