For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis
Sungsoo CHOI Kiseon KIM
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/11/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
finite field, standard basis, multiplier-first inversion circuit (MFIC), square-first inversion circuit (SFIC),
Full Text: PDF>>
To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in , as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.