Analysis of IDDQ Occurrence in Testing

Arabi KESHK  Yukiya MIURA  Kozo KINOSHITA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E84-D   No.4   pp.534-536
Publication Date: 2001/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System Element
Keyword: 
IDDQ testing,  bridging fault,  fault analysis,  

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Summary: 
This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.