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The Evolutionary Algorithm-Based Reasoning System
Moritoshi YASUNAGA Ikuo YOSHIHARA Jung Hwan KIM
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems)
evolutionary algorithm, reasoning, FPGA, wafer scale integration, fault tolerance,
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In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.