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Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC
Joon-Seok LEE Se-Hoon JOO Seung-Hoon LEE
IEICE TRANSACTIONS on Electronics
Publication Date: 2001/08/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
calibration, ADC, CFCS, high-resolution,
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This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.