Low Power CMOS Design Challenges

Tadahiro KURODA  

IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.8   pp.1021-1028
Publication Date: 2001/08/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Silicon Nanodevices)
low power CMOS design,  low voltage,  threshold voltage,  subthreshold leakage current,  downsizing,  

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Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.