Summary
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An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems Toshiaki INOUE Takashi MANABE Sunao TORII Satoshi MATSUSHITA Masato EDAHIRO Naoki NISHI Masakazu YAMASHINA Publication IEICE TRANSACTIONS on Electronics Vol.E84-C No.8 pp.1014-1020 Publication Date: 2001/08/01 Online ISSN: DOI: Print ISSN: 0916-8516 Type of Manuscript: Special Section INVITED PAPER (Special Issue on Silicon Nanodevices) Category: Keyword: SIMD, multiplier, embedded microprocessor, on-chip multiprocessor, area-efficiency, Full Text: PDF(2.5MB)>>
Summary: We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology. | |||||
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